This invention relates in general to time delay circuits, and more particularly to an electrical circuit for time delay of signals to an integrated circuit and having low sensitivity to changes in supply voltage and ambient temperature.
Time delay circuits are widely used in digital and mixed signal chips for providing delay adjustments of clock signals in digital systems where speed is a critical factor. In mixed signal chips, for example, delay elements are used in analog to digital converters for sampling clock phase optimization, such as required when converting time-referenced analog signals (e.g. graphics and video signals). A digital display controller with analog interface satisfying the requirements for different display environments requires a circuit that provides a wide delay range with sub-gate delay steps. A specific display environment may require very fine delay steps whereas other display environments may require coarse steps in performing phase adjustments for the time reference signals. Furthermore, to achieve an acceptable display image, variation in absolute delay values, caused by variations in operating conditions, should be limited.
Time delay circuits have been implemented using inverter chain and RC-delay techniques as these techniques offer simple and easy solutions. These circuits suffer from many disadvantages, as the time delays are highly sensitive to operating conditions such as supply voltage and ambient temperature. Also, when such circuits are used in a noisy environment performance is degraded and consequently, display image quality is degraded. Attempts have been made to provide delay circuits using CMOS thyristors. Although such circuits exhibit improved sensitivity to environmental conditions, the sensitivity of the CMOS thyristors is still not acceptable for display image processing.
Other implementations of delay circuits, with improved performance characteristics generally involve complex designs using PLL or interpolation techniques in closed loop systems. These circuits suffer the disadvantages of consuming large area and static power when a wide delay range is required.
It is therefore desirable to provide a circuit for time delay of signals to an integrated circuit, which is characterized by low sensitivity to changes in supply voltage and ambient temperature.
In accordance with an aspect of the present invention, there is provided a programmable delay element for delaying a digital input signal, comprising a discharge capacitor adapted to be precharged to a predetermined voltage in response to a first transition of the digital input signal. A transistor switch of a first type is provided for precharging the discharge capacitor to a predetermined voltage. A discharge current source is connected via a sense node to the discharge capacitor for discharging the capacitor in response to a subsequent opposite transition of the digital input signal. A transistor switch of a second type is provided for connecting the discharge capacitor to the discharge current source and thereby discharging the discharge capacitor. A reference voltage source is provided for applying a reference voltage to a reference node. A comparator is provided having a first input connected to the sense node and a second input connected to the reference node, such that an output of the comparator generates a delayed version of the digital input signal such that the subsequent opposite transition is delayed by an amount equal to the time for the capacitor to discharge to a voltage equal to the reference voltage.